Display Omitted A method for the extraction of the interface trap density is proposed.The energetic distribution of the traps is obtained through the method.The method is validated using numerical simulations.The accuracy of the determination of both trap densities and energy is studied.Experimental JNTs with different gate stack and doping concentration were analyzed. This work proposes a method for extracting the energetic distribution of the interface trap density at the gate dielectric in Junctionless silicon Nanowire Transistors. The proposed method uses the subthreshold slope extraction combined with the substrate bias in order to induce a variation in the channel potential, such that the interface trap density can be extracted for a significant energy range. Three-dimensional TCAD numerical simulations have been performed to analyze the accuracy of the proposed method considering different concentrations and trap density profiles (uniform and exponential). The influence of the device width variation on the trap energy determination has been analyzed, showing that only for positive substrate biases the energy might be affected. The method precision was also analyzed, showing that the trap density extraction is only effectively affected for low Nit values, which do not influence significantly the device performance. Finally, the method has been applied to experimental transistors with high-Â? and silicon dioxide gate dielectrics showing consistent results.
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