Core Reliability: Leveraging Hardware Transactional Memory

Modern microprocessors are more vulnerable to transient faults or soft errors than ever before due to design trends mandating low supply voltage and reduced noise margins, shrinking feature sizes and increased transistor density for fast, low-power circuits. As industry now supports Hardware Transactional Memory (HTM), the features of HTM can be leveraged to add core resiliency to transient errors. In this paper, we propose a novel microarchitecture for transient error detection and recovery based on time redundancy and backward error recovery leveraging HTM's existing features especially its rollback mechanism. We provide implementation details for single-core reliability, minimizing additions to existing HTM supports. We evaluate the performance overheads of the single core with the reliability feature by comparing it to the base machine without the reliability feature. Finally we show how single-core reliability can be extended to multi-core reliability.