Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latch-up and inter-power supply latch-up in advanced CMOS technologies

CMOS latch-up has historically been a problem in bulk CMOS processes through a parasitic pnpn structure formed by parasitic pnp and npn bipolar transistors. In application systems, latch-up is a dominant failure mode that causes either soft failure due to a loss of data logic states or destructive failure of the system. In this paper, the authors focused on cases of I/O VDD to core VDD latch-up and other cross "book" latch-up; the significance of this work shows that in 0.13 and sub-0.13 mum technologies, CMOS latch-up can occur between different VDD power supplies and between chip sub-functions. This work advances the CMOS technology by addressing chip-level layout, critical bias considerations, as well as and in conjunction with unit I/O cell level latch-up considerations for preventing neighboring I/O-to-I/O cell interaction-induced latch-up. Additionally, emission microscope (EMMI) techniques and latch-up simulation results were shown.

[1]  J. Slinkman,et al.  Retrograde well and epitaxial thickness optimization for shallow- and deep-trench collar merged isolation and node trench SPT DRAM cell and CMOS logic technology , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[2]  Steven H. Voldman.  A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup , 2005, Microelectron. Reliab..

[3]  L. Lanzerotti,et al.  The influence of heavily doped buried layer implants on electrostatic discharge (ESD), latchup, and a silicon germanium heterojunction bipolar transistor in a BiCMOS SiGe technology , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[4]  Ronald R. Troutman.  Latchup in CMOS Technology , 1986 .

[5]  T. Suzuki,et al.  ESD and latch-up characteristics of semiconductor device with thin epitaxial substrate , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[6]  R. Troutman,et al.  Epitaxial layer enhancement of n-well guard rings for CMOS circuits , 1983, IEEE Electron Device Letters.

[7]  Ming-Dou Ker,et al.  Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs , 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

[8]  T. Nakamura,et al.  Latch-up immunity against noise pulses in a CMOS double well structure , 1983, 1983 International Electron Devices Meeting.

[9]  A. Watson,et al.  The influence of deep trench and substrate resistance on the latchup robustness in a BiCMOS silicon germanium technology , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[10]  C. Duvvury,et al.  Impact of scaling on the high current behavior of RF CMOS technology , 2004, IEEE Transactions on Device and Materials Reliability.

[11]  Hsiao-Yi Lin,et al.  Improvement of CMOS latch-up immunity using a high energy implanted buried layer , 1989 .

[12]  C. Duvvury,et al.  A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[13]  Donald B. Estreich.  The physics and modeling of latch-up and CMOS integrated circuits , 1980 .

[14]  B. L. Gregory,et al.  Latch-Up in CMOS Integrated Circuits , 1973 .

[15]  S.H. Voldman.  The effect of deep trench isolation, trench isolation and sub-collector doping on the electrostatic discharge (ESD) robustness of radio frequency (RF) ESD STI-bound P+/N-well diodes in BiCMOS silicon germanium technology , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[16]  W. Morris,et al.  Latchup in CMOS , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[17]  Steven H. Voldman,et al.  MeV implants boost device design , 1995 .

[18]  J. Harter,et al.  Comparison of latch-up in p- and n-well CMOS circuits , 1983, 1983 International Electron Devices Meeting.

[19]  A. Ochoa,et al.  An analysis of latch-up prevention in CMOS IC's using an epitaxial-buried layer process , 1978, 1978 International Electron Devices Meeting.

[20]  H.P. Zappe,et al.  A transient analysis of latchup in bulk CMOS , 1983, IEEE Transactions on Electron Devices.

[21]  E. Gebreselasie,et al.  The influence of a silicon dioxide-filled trench isolation structure and implanted sub-collector on latchup robustness , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[22]  Ming-Dou Ker,et al.  How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on , 1999 .

[23]  Charvaka Duvvury,et al.  Impact of scaling on the high current behavior of RF CMOS technology , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[24]  A. Watson,et al.  The effect of deep trench and sub-collector on the latchup robustness in BiCMOS silicon germanium technology , 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.