Implementation of high VT turn-on in low-voltage SCR devices

A novel design approach for low-voltage ESD protection clamps is suggested based on the use of free pseudo high threshold voltage SCR structures. The method is experimentally validated for a 0.18 mum 1.8 V/5 V dual gate oxide CMOS process where free high threshold voltage (VT) LVTSCR and Drain extended NMOS-SCR structures were formed by combining the thick 120 A gate oxide used for 5 V devices with additional low voltage PWELL through poly implants used for the 1.8 V devices. The physical mechanism of the forming of pseudo high VT characteristics is explained by means of numerical simulation. Low-voltage pulsed turn-on and turn-off characteristics have been demonstrated under low DC leakage of the devices.

[1]  V.A. Vashchenko,et al.  ESD protection of double-diffusion devices in submicron CMOS processes , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[2]  V.A. Vashchenko,et al.  ESD protection window targeting using LDMOS-SCR devices with PWELL-NWELL super-junction , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[3]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[4]  Taylor R. Efland,et al.  SCR-LDMOS. A novel LDMOS device with ESD robustness , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[5]  A. Amerasekera,et al.  Bipolar SCR ESD protection circuit for high speed submicron bipolar/BiCMOS circuits , 1995, Proceedings of International Electron Devices Meeting.

[6]  Vladislav A. Vashchenko,et al.  Bipolar SCR ESD devices , 2005, Microelectron. Reliab..

[7]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[8]  Timothy J. Maloney,et al.  Basic ESD and I/O Design , 1998 .