OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents OrthoNoC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, OrthoNoC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of OrthoNoC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of OrthoNoC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of OrthoNoC goes beyond simply improving the performance of the on-chip interconnect.

[1]  Jason Cong,et al.  A scalable micro wireless interconnect structure for CMPs , 2009, MobiCom '09.

[2]  David Blaauw,et al.  Scaling towards kilo-core processors with asymmetric high-radix topologies , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[3]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[4]  Theodore S. Rappaport,et al.  On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems , 2009, IEEE Journal on Selected Areas in Communications.

[5]  Eduard Alarcón,et al.  Characterization and modeling of multicast communication in cache-coherent manycore processors , 2016, Comput. Electr. Eng..

[6]  Theodore S. Rappaport,et al.  On-Chip Integrated Antenna Structures in CMOS for 60 GHz WPAN Systems , 2009, GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference.

[7]  Li-Shiuan Peh,et al.  Single-cycle collective communication over a shared network fabric , 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[8]  George Kurian,et al.  ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[9]  George Michelogiannakis,et al.  An analysis of on-chip interconnection networks for large-scale chip multiprocessors , 2010, TACO.

[10]  Josep Torrellas,et al.  A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip , 2016, NoCArc'16.

[11]  David W. Matolak,et al.  Kilo-core Wireless Network-on-Chips (NoCs) Architectures , 2015, NANOCOM.

[12]  Chen Sun,et al.  DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[13]  David R. Kaeli,et al.  Multi2Sim: A simulation framework for CPU-GPU computing , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[14]  Bipin Rajendran,et al.  Characterization and Modeling , 2017 .

[15]  Raymond G. Beausoleil,et al.  Nanoelectronic and Nanophotonic Interconnect , 2008, Proceedings of the IEEE.

[16]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[17]  Mauricio Hanzich,et al.  Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach , 2015, IEEE Micro.

[18]  Anantha Chandrakasan,et al.  SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[19]  Partha Pratim Pande,et al.  Multicast-Aware High-Performance Wireless Network-on-Chip Architectures , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Vwani P. Roychowdhury,et al.  RF/wireless interconnect for inter- and intra-chip communications , 2001, Proc. IEEE.

[21]  Christof Teuscher,et al.  Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems , 2011, IEEE Transactions on Computers.

[22]  Eduard Alarcón,et al.  On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration , 2015, IEEE/ACM Transactions on Networking.

[23]  Luca P. Carloni,et al.  PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[24]  Hannu Tenhunen,et al.  A generic adaptive path-based routing method for MPSoCs , 2011, J. Syst. Archit..

[25]  Li-Shiuan Peh,et al.  Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[26]  Ahmed Louri,et al.  OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures , 2015, 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects.

[27]  Masoud Daneshtalab,et al.  Routing Algorithms in Networks-on-Chip , 2013 .

[28]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[29]  Rajeev J. Ram,et al.  Single-chip microprocessor that communicates directly using light , 2015, Nature.

[30]  Jim D. Garside,et al.  Overview of the SpiNNaker System Architecture , 2013, IEEE Transactions on Computers.

[31]  Corrado Carta,et al.  A Low-Power SiGe BiCMOS 190-GHz Transceiver Chipset With Demonstrated Data Rates up to 50 Gbit/s Using On-Chip Antennas , 2017, IEEE Transactions on Microwave Theory and Techniques.

[32]  David W. Matolak,et al.  A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[33]  Eran Socher,et al.  9mW 6Gbps bi-directional 85–90GHz transceiver in 65nm CMOS , 2014, 2014 9th European Microwave Integrated Circuit Conference.

[34]  Manfred Glesner,et al.  Multicast Parallel Pipeline Router Architecture for Network-on-Chip , 2008, 2008 Design, Automation and Test in Europe.

[35]  Onur Mutlu,et al.  Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[36]  David W. Matolak,et al.  A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors , 2015, IEEE Transactions on Parallel and Distributed Systems.

[37]  Pat Conway,et al.  The AMD Opteron Northbridge Architecture , 2007, IEEE Micro.

[38]  Zheng Wang,et al.  A CMOS 210-GHz Fundamental Transceiver With OOK Modulation , 2014, IEEE Journal of Solid-State Circuits.

[39]  Anantha Chandrakasan,et al.  Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI , 2012, DAC Design Automation Conference 2012.

[40]  Partha Pratim Pande,et al.  Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects , 2013, IEEE Transactions on Computers.

[41]  Vincenzo Catania,et al.  Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[42]  Norman P. Jouppi,et al.  CACTI 6.0: A Tool to Model Large Caches , 2009 .

[43]  Josep Torrellas,et al.  WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication , 2016, ASPLOS.

[44]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[45]  Terrence Mak,et al.  A Survey of Emerging Interconnects for On-Chip Efficient Multicast and Broadcast in Many-Cores , 2016, IEEE Circuits and Systems Magazine.

[46]  Davide Bertozzi,et al.  The fast evolving landscape of on-chip communication , 2015, Des. Autom. Embed. Syst..

[47]  Partha Pratim Pande,et al.  Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[48]  Milos Prvulovic,et al.  Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect , 2013, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques.

[49]  Eduard Alarcón,et al.  Scalability of Broadcast Performance in Wireless Network-on-Chip , 2016, IEEE Transactions on Parallel and Distributed Systems.