Heterogeneous MP-SoC - the solution to energy-efficient signal processing
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[1] Rainer Leupers,et al. Architecture exploration for embedded processors with LISA , 2002 .
[2] Jon Connell. Early Hardware / Software Integration Using SystemC 2 . 0 , 2002 .
[3] Rainer Leupers,et al. A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[4] Rainer Leupers,et al. A modular simulation framework for architectural exploration of on-chip interconnection networks , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[5] Takayuki Sasaki,et al. A practical approach for bus architecture optimization at transaction level , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[6] Dean M. Tullsen,et al. Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.
[7] Mayan Moudgill,et al. A Multithreaded Processor Architecture for SDR , 2002 .
[8] G. Braun,et al. A universal technique for fast and flexible instruction-set architecture simulation , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[9] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[10] Ahmed Amine Jerraya,et al. Unified component integration flow for multi-processor SoC design and validation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[11] Luciano Lavagno,et al. Metropolis: An Integrated Electronic System Design Environment , 2003, Computer.
[12] Heinrich Meyr,et al. Design of Energy-Efficient Application-Specific Instruction Set Processors , 2004 .
[13] Ravi Subramanian,et al. Novel application-specific signal processing architectures for wideband CDMA and TDMA applications , 2000, VTC2000-Spring. 2000 IEEE 51st Vehicular Technology Conference Proceedings (Cat. No.00CH37026).
[14] Holger Blume,et al. Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip , 2005, J. VLSI Signal Process..
[15] Rainer Leupers,et al. Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs , 2008, SAMOS.
[16] T.A.C.M. Claasen. High speed: not the only way to exploit the intrinsic computational power of silicon , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[17] Torsten Kempf,et al. A highly efficient modeling style for heterogeneous bus architectures , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).
[18] Jan Madsen,et al. Abstract RTOS modeling for multiprocessor system-on-chip , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).
[19] Thorsten Grotker,et al. System Design with SystemC , 2002 .
[20] Laurent Maillet-Contoz,et al. TRANSACTION LEVEL MODELING An Abstraction Beyond RTL , 2005 .
[21] Andy D. Pimentel,et al. An IDF-based trace transformation method for communication refinement , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[23] Pierre G. Paulin,et al. System-on-chip beyond the nanometer wall , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[24] Miltos D. Grammatikakis,et al. Software for Multiprocessor Networks on Chip , 2003, Networks on Chip.
[25] Kees G. W. Goossens,et al. Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[26] Daniel D. Gajski,et al. SPECC: Specification Language and Methodology , 2000 .
[27] K. Keutzer,et al. System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[28] Om Prakash Gangwal,et al. A Heterogeneous Multiprocessor Architecture for Flexible Media Processing , 2002, IEEE Des. Test Comput..
[29] Andreas Gerstlauer,et al. RTOS scheduling in transaction level models , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[30] G. G. Stokes. "J." , 1890, The New Yale Book of Quotations.
[31] Daniel Gajski,et al. Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).