Delay analysis of a single voltage‐scaled‐repeater driven long interconnect

Purpose – To study the effect of voltage‐scaling on output voltage waveform, delay and power dissipation in a single inverter/repeater driven interconnect load, in different technology nodes.Design/methodology/approach – An analytical expression for the output voltage of a single CMOS‐inverter/repeater driven long interconnects is developed. Delay analysis by the use of this expression, for long interconnects, modeled as RLC load, is compared with SPICE simulations. Good agreement between analytical and SPICE derived results is obtained.Findings – The model works well for both sub‐micron and nanometer CMOS technologies. The maximum error in 90 percent fall time of output voltage is 7.5, 2.6 and 0.28 percent in 0.8 μm, 0.18 μm and 70 nm technologies, respectively. The maximum inaccuracy in case of high to low 50 percent propagation delay is about 5 percent for 0.8 μm, 3.1 percent for 0.18 μm and 2.3 percent in case of 70 nm technologies. The model shows a very good accuracy for nanometer technologies. The ...

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