Application-Specific Topology Design Customization for STNoC
暂无分享,去创建一个
[1] M. Coppola,et al. Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[2] Radu Marculescu,et al. Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach , 2005, Design, Automation and Test in Europe.
[3] M. Gail Jones,et al. It's a Small World After All. , 2005 .
[4] Srinivasan Murali,et al. A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[5] Piotr Czyzżak,et al. Pareto simulated annealing—a metaheuristic technique for multiple‐objective combinatorial optimization , 1998 .
[6] William J. Dally,et al. Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.
[7] Gianluca Palermo,et al. PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures , 2004, PATMOS.
[8] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[9] Srinivasan Murali,et al. An Application-Specific Design Methodology for STbus Crossbar Generation , 2005, Design, Automation and Test in Europe.
[10] Radu Marculescu,et al. "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.