Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology

A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of −8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.

[1]  R. Stahlmann,et al.  Dual-Gate MESFET Mixers , 1984 .

[2]  Youngwoo Kwon,et al.  High-performance V-band cascode HEMT mixer and downconverter module , 2003 .

[3]  R.W. Brodersen,et al.  A 60-GHz down-converting CMOS single-gate mixer , 2005, 2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers.

[4]  H.-Y. Chang,et al.  A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13-/spl mu/m CMOS technology , 2006, IEEE Microwave and Wireless Components Letters.

[5]  M. Fujishima,et al.  60-GHz CMOS Down-Conversion Mixer with Slow-Wave Matching Transmission Lines , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[6]  Theodore S. Rappaport,et al.  Short-Range Wireless Communications for Next-Generation Networks: UWB, 60 GHz Millimeter-Wave WPAN, And ZigBee , 2007, IEEE Wireless Communications.

[7]  W. Keusgen,et al.  60 GHz SiGe HBT downconversion mixer , 2007, 2007 European Microwave Integrated Circuit Conference.

[8]  Chung-Yu Wu,et al.  The Design of Low LO-Power 60-GHz CMOS Quadrature-Balanced Self-Switching Current-Mode Mixer , 2008, IEEE Microwave and Wireless Components Letters.