Input/output complexity of bit-level VLSI array architectures

[1]  Louis L. Scharf,et al.  VLSI design of inner-product computers using distributed arithmetic , 1989, IEEE International Symposium on Circuits and Systems,.

[2]  L. L. Scharf,et al.  A systolic VSLI chip for implementing orthogonal transforms , 1989 .

[3]  Marina C. Chen,et al.  The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI , 1988, IEEE Trans. Computers.

[4]  Sailesh K. Rao,et al.  What is a Systolic Algorithm? , 1986, Photonics West - Lasers and Applications in Science and Engineering.

[5]  S. Smith,et al.  Efficient bit-serial complex multiplication and sum-of-products computation using distributed arithmetic , 1986, ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[6]  John V. McCanny,et al.  Bit-level systolic array circuit for matrix vector multiplication , 1983 .

[7]  Jean Vuillemin,et al.  A Combinatorial Limit to the Computing Power of VLSI Circuits , 1983, IEEE Transactions on Computers.

[8]  Bede Liu,et al.  A new hardware realization of digital filters , 1974 .