Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

A highly-digital clock multiplication architecture that achieves excellent jitter and mitigates supply noise is presented. The proposed architecture utilizes a calibration-free digital multiplying delay-locked loop (MDLL) to decouple the tradeoff between time-to-digital converter (TDC) resolution and oscillator phase noise in digital phase-locked loops (PLLs). Both reduction in jitter accumulation down to sub-picosecond levels and improved supply noise rejection over conventional PLL architectures is demonstrated with low power consumption. A digital PLL that employs a 1-bit TDC and a low power regulator that seeks to improve supply noise immunity without increasing loop delay is presented and used to compare with the proposed MDLL. The prototype MDLL and DPLL chips are fabricated in a 0.13 μm CMOS technology and operate from a nominal 1.1 V supply. The proposed MDLL achieves an integrated jitter of 400 fs rms at 1.5 GHz output frequency from a 375 MHz reference clock, while consuming 890 μ W. The worst-case supply noise sensitivity of the MDLL is 20 fspp/mVpp which translates to a jitter degradation of 3.8 ps in the presence of 200 mV supply noise. The proposed clock multipliers occupy active die areas of 0.25 mm2 and 0.2 mm2 for the MDLL and DPLL, respectively.

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