Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops

This paper describes the design of a low-power pipelined multiplier. It is illustrated in this paper that the power consumption of the clocking system cannot be overlooked and the design of the storage element is the key to low power. A new pulse-triggered true single-phase clocking (TSPC) flip-flop (PTTFF) is proposed for this purpose in this design. The PTTFF features true single-phase clocking, simple structure, and high performance. One PTTFF comprises only five transistors with only one controlled by the clock. Using the PTTFF together with the 14-transistor pseudo-NMOS full adder, an 8-b/spl times/8-b pipelined multiplier has been designed and implemented, employing a 0.6-/spl mu/m CMOS process. When the multiplier operates at the operating frequency of 300 MHz with VDD equal to 3.3 V, it dissipates only 53% of the power of the multiplier designed with nine-transistor TSPC flip-flops under the same operating conditions. When the supply voltage for the core array is reduced to 2.5 V, the multiplier can still work up to 300 MHz with only 47% of the power of the multiplier designed using the S and D full adders and C/sup 2/MOS latches with VDD equal to 3.3 V. The chip has been fabricated, and the measured power is 52.4 mW when operated at 300 MHz and 3.3 V.

[1]  Jinn-Shyan Wang,et al.  A pulse-triggered TSPC flip-flop for high-speed low-power VLSI design applications , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[2]  Sung-Mo Kang.  Accurate simulation of power dissipation in VLSI circuits , 1986 .

[3]  Shyh-Jye Jou,et al.  A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design , 1995 .

[4]  M.T. Fertsch,et al.  A 16 bitx16 bit pipelined multiplier macrocell , 1985, IEEE Journal of Solid-State Circuits.

[5]  E. Abu-Shama,et al.  A new cell for low power adders , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[6]  Jinn-Shyan Wang.  A new true-single-phase-clocked double-edge-triggered flip-flop for low-power VLSI designs , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[7]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[8]  Christer Svensson,et al.  A unified single-phase clocking scheme for VLSI systems , 1990 .

[9]  Gerald E. Sobelman,et al.  A new low-voltage full adder circuit , 1997, Proceedings Great Lakes Symposium on VLSI.

[10]  N. F. Goncalves,et al.  NORA: a racefree dynamic CMOS technique for pipelined logic structures , 1983 .

[11]  M. Hatamian,et al.  A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS , 1986 .

[12]  D. Schmitt-Landsiedel,et al.  A Pipelined 330 MHz Multiplier , 1985, ESSCIRC '85: 11th European Solid-State Circuits Conference.

[13]  Dinesh Somasekhar,et al.  A 230 MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking , 1993, The Sixth International Conference on VLSI Design.

[14]  H. Samueli,et al.  A 200 MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design , 1993 .