An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications

Key elements for machine vision are the intra-scene dynamic range of the optical front-end, and a data representation that is as independent as possible from the illumination level. Furthermore, combining an optical front-end and a processor on the same chip enables a single-chip vision system to perform image acquisition, analysis and decision-making. Approaches that enable high dynamic range are logarithmic imagers [1] and lin-log imagers [2], but they suffer from poor fixed-pattern noise (FPN) performance [1,2] and non-uniform transfer functions [2] due to the combination of linear and logarithmic domains. While multiple-exposure imagers [3] solve the FPN problem, they require post-processing to combine several frame captures. Finally the dynamic range of time-domain logarithmic imagers with fixed reference voltages [4] is limited by the maximum allowable exposure time.

[1]  S. Kavadias,et al.  A logarithmic response CMOS image sensor with on-chip calibration , 2000, IEEE Journal of Solid-State Circuits.

[2]  Pierre-Yves Burgi,et al.  A 128 /spl times/ 128 pixel 120 dB dynamic range vision sensor chip for image contrast and orientation extraction , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  S. Komori,et al.  A linear-logarithmic CMOS sensor with offset calibration using an injected charge signal , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[4]  C. Piguet,et al.  Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[5]  A. Bermak,et al.  A novel adaptive logarithmic digital pixel sensor , 2006, IEEE Photonics Technology Letters.

[6]  D. Schmitt-Landsiedel,et al.  A 128 /spl times/ 128 CMOS bio-sensor array for extracellular recording of neural activity , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[7]  A. El Gamal,et al.  A 0.18 /spl mu/m high dynamic range NTSC/PAL imaging system-on-chip with embedded DRAM frame buffer , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..