Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications

In an orthogonal frequency division multiplexing (OFDM)-based digital transmitter, the inverse fast Fourier transform (IFFT) processing unit consumes the most hardware area and power, especially because of the twiddle multipliers in the Cooley–Tukey-based decimation-infrequency (DIF) IFFT architecture. This work concentrates on the trivial multiplications in the input stage of the IFFT unit and replaces them by the proposed ‘pass-logic’. These replacements can be possible because the inputs are bitwise with binary-phase shift keying (PSK) or qudrature-PSK digital modulation. The input stage of DIF-FFT for 8 to 128 points (N) were implemented with multipliers and ‘pass-logics’. The performance improvements (PIs) of the proposed FFT/IFFT implementation have been analysed. For a 64-point FFT in FPGA, the number of slices was reduced by 9% and the total power by 6.5%. The same implementation on an ASIC, consumed 28% less power and 27% lesser gates. In 128-point implementation, these PIs are more than those of the 64-point, thus PI is in upward trend as N increases. A chip for FFT processing as per IEEE 802.11a specifications (64-point, 16-bit data) is designed with pass-logics, which uses 24 947 gates and consumes 6.45 mW at 1.8 V, 20 MHz in 0.18 µm 1P6M CMOS process.