论文信息 - Design and Implementation of a Reaction Timer Using CMOS Logic

Design and Implementation of a Reaction Timer Using CMOS Logic

This paper presents an overview of a reaction timer having an accuracy up to two decimal places (which is extendable). Three decade counters constitute the circuitry of this reaction timer wherein each of the decade counters is connected to four master–slave J-K flip-flops to form a sequential circuit. A delay signal is also introduced at the input so that the output is genuine. The whole simulation process is carried out in Cadence virtuoso analog and digital design environment of gpdk045 nm CMOS technology at a supply voltage of 1 V.

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