论文信息 - Computer Reduction of Two-Level, Multiple-Output Switching Circuits - 字舞流文

Computer Reduction of Two-Level, Multiple-Output Switching Circuits

An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.

Donald L. Dietmeyer | Yueh-Hsung Su

[1] G. C. Vandling. The Simplification of Multiple-Output Switching Networks Composed of Unilateral Devices , 1960, IRE Trans. Electron. Comput..

[2] R. McNaughton,et al. The minimality of rectifier nets with multiple outputs incompletely specified , 1957 .

[3] Donald L. Dietmeyer,et al. Logic Design Automation of Fan-In Limited NAND Networks , 1969, IEEE Transactions on Computers.

[4] Yueh-Hsung Su. Computer oriented algorithms for synthesizing multiple output combinational and finite memory sequential circuits , 1967 .

[5] Thomas C. Bartee,et al. Computer Design of Multiple-Output Logical Networks , 1961, IRE Trans. Electron. Comput..

[6] David E. Muller,et al. Application of Boolean algebra to switching circuit design and to error detection , 1954, Trans. I R E Prof. Group Electron. Comput..

[7] J. Roth. Algebraic topological methods for the synthesis of switching systems. I , 1958 .

[8] Donald L. Dietmeyer,et al. Identification of Symmetry, Redundancy and Equivalence of Boolean Functions , 1967, IEEE Trans. Electron. Comput..