Simulating resistive bridging and stuck-at faults

We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.

[1]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[2]  Tracy Larrabee,et al.  Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.

[3]  Siyad C. Ma,et al.  A comparison of bridging fault simulation methods , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[4]  Michele Favalli,et al.  Bridging fault modeling and simulation for deep submicron CMOS ICs , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[6]  John M. Acken,et al.  Fault Model Evolution For Diagnosis: Accuracy vs Precision , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[7]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[8]  Bernd Becker,et al.  Efficient bridging fault simulation of sequential circuits based on multi-valued logics , 2002, Proceedings 32nd IEEE International Symposium on Multiple-Valued Logic.

[9]  D. M. H. Walker,et al.  PROBE: a PPSFP simulator for resistive bridging faults , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[10]  Michele Favalli,et al.  Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[11]  Tristan Derème.  Test en tension des courts-circuits en technologie CMOS , 1995 .

[12]  Heinrich Theodor Vierhaus,et al.  CMOS bridges and resistive transistor faults: IDDQ versus delay effects , 1993, Proceedings of IEEE International Test Conference - (ITC).

[13]  D. M. H. Walker,et al.  Accurate fault modeling and fault simulation of resistive bridges , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).