Hardware synthesis with the Bach system

We describe the Bach hardware synthesis system from parallel algorithms, allowing users to design, verify and synthesize large and complex circuits. Each is a working tool which is already being used for full-scale commercial designs. The source language is based on ANSI C with extensions to support explicit parallelism, communications and bit-width specification. We demonstrate its effectiveness by evaluating industrial strength applications.

[1]  Giovanni De Micheli,et al.  Synthesis of ASICs with Hercules and Hebe , 1991 .

[2]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[3]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[4]  C. A. R. Hoare,et al.  Communicating Sequential Processes (Reprint) , 1983, Commun. ACM.

[5]  Michel Auguin,et al.  A partitioning algorithm for system-level synthesis , 1992, ICCAD.

[6]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[7]  Takashi Kambe,et al.  A scheduling method for synchronous communication in the Bach hardware compiler , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[8]  Stan Y. Liao,et al.  An efficient implementation of reactivity for modeling hardware in the scenic design environment , 1997, DAC.

[9]  Edward A. Lee,et al.  A hardware-software codesign methodology for DSP applications , 1993, IEEE Design & Test of Computers.

[10]  Jörg Henkel,et al.  Hardware-software cosynthesis for microcontrollers , 1993, IEEE Design & Test of Computers.

[11]  Michel Auguin,et al.  A partitioning algorithm for system-level synthesis , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.