论文信息 - Design considerations and tools for low-voltage digital system design

Design considerations and tools for low-voltage digital system design

Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology trends for low-voltage operation are presented including low-threshold devices, multiple-threshold devices, and SOI and bulk-CMOS based variable threshold devices. The requirements on CAD tools that allow designers to choose and optimize various technology, circuit, and system parameters are also discussed.

Anantha Chandrakasan | Dimitri Antoniadis | Carlin Vieri | Isabel Y. Yang

[1] Marios C. Papaefthymiou,et al. Precomputation-based sequential logic optimization for low power , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[2] Mani B. Srivastava,et al. Predictive system shutdown and other architectural techniques for energy efficient programmable computation , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[3] H. Hara,et al. 50% active-power saving without speed degradation using standby power reduction (SPR) circuit , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[4] Dimitri A. Antoniadis,et al. Back gated CMOS on SOIAS for dynamic threshold voltage control , 1995, Proceedings of International Electron Devices Meeting.

[5] Thomas J. Barber. Bodylantm: a Low-power Communications System Bodylantm: a Low-power Communications System , 1996 .

[6] Takeshi Sakata,et al. Subthreshold-current reduction circuits for multi-gigabit DRAM's , 1994 .

[7] Amitabh Srivastava,et al. Analysis Tools , 2019, Public Transportation Systems.

[8] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .