Physics-Based Low-Cost Test Technique for High Voltage LDMOS

This paper presents a low-cost test technique for testing high-voltage laterally diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to identify structural defects such as gate-FOX breakdown, post breakdown thermal stress and drain leakage due to high voltages. A novel highly accurate hybrid MOS-p model for HV-LDMOS was developed and validated across various device geometries including both long and small gate-channels. Structural defects in HV-LDMOS were modeled and their physical effect was induced in the hybrid MOS-p model to develop fault models. These fault models were used for parametric testing and diagnosis of HV-LDMOS. A novel test technique using a noise-reduction scheme to test HV-LDMOS is presented in this paper. Test simulations were performed on a MOSFET driver IC with a 700 V LDMOS and experimental validation was performed by building a prototype test setup and making hardware measurements for breakdown and leakage tests. This test technique overcomes the test challenges pertaining to power supply and tester system noise, and provides a superior signal-to-noise ratio (SNR) when compared to conventional test methods. The noise-reduction scheme is inexpensive and highly accurate. The fault-model based test approach reduces the test suite for HV-LDMOS to a couple of test measurements which reduces the overall test cost and time.