On a standard approach for substrate noise modelling in mixed signal IC's

An alternative way of using the ICEM model is described. This model is considering each part of a mixed signal design: the PCB, the package, the bonding wires, the padring and the core of the digital chip. By adding some elements to this model, we can simulate the transient substrate voltage induced by the digital part of a mixed signals integrated circuit. A test-chip was implemented in a 0.35 /spl mu/m BiCMOS process to validate this extended ICEM model. Some spice simulations of the modelled test-chip, running in many different configurations, are exposed. The results of those simulations are compared to measurements and reveal the advantages and drawbacks points of the methodology. We also describe what has to be done to apply this method to a realistic digital circuit.

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