Silicon Bipolar Demultiplexer/Decision Circuit for Gigabit Optical Communication Systems
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A silicon bipolar IC for the receiving end of a gigabit fiber optic trunk line is presented, performing both demultiplexing and decision functions. The circuit is based on a 2 ¿m non-self-aligned silicon technology. At 4 Gb/s the measured clock-phase-margin (CPM) is about 120 degrees, related to an ideal CPM of 180 degrees. Differential input sensitivity at 4 Gb/s is less than 150 mV.
[1] D. Clawin,et al. Multigigabit/second silicon decision circuit , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2] H.-M. Rein,et al. A bipolar 4:1 time division multiplexer IC operating up to 5.5Gb/s , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.