A thorough investigation into active and passive shielding methods for nano-VLSI interconnects against EMI and crosstalk

Abstract In this study two main shielding methodologies, active and passive, are comprehensively investigated for crosstalk and EMI alleviation. Electromagnetic coupling is a major concern for digital system wiring. It can cause logic fault, consume power and make signal integrity problem for neighbor wires. Active and passive shielding is employed to enclose partially some important wires like CLOCK network. Passive shield, which is a line connected to POWER rail or the GROUND, can enforce extra delay to the concerned wire. Rather, active shield is used to gain both guarding effect and reduction in time delay based on Miller's effect capacitance reduction. With area constraint for both silicon and metal, we have optimized which methodology should be chosen for best achievable performance. With simple analytic steps, the accuracy is verified and a design approach is introduced to choose the best. In addition, the immunity of the active and passive shield is studied against external electromagnetic wave. The result concludes that the passive shield show a better resistance in front of electromagnetic coupling, for both near pairing (crosstalk) and distant coupling (incident electromagnetic wave); in addition, active shielding method has better characteristic for timing issues.

[1]  Hector Sanchez,et al.  A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .

[2]  David Blaauw,et al.  Performance optimization of critical nets through active shielding , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Brajesh Kumar Kaushik,et al.  Effect of aggressor driver width on crosstalk for static and dynamic switching of victim line , 2010, 2010 International Conference on Computer and Communication Technology (ICCCT).

[4]  V. Rajamani,et al.  A New ANN-Based Modeling Approach for Rapid EMI/EMC Analysis of PCB and Shielding Enclosures , 2013, IEEE Transactions on Electromagnetic Compatibility.

[5]  Dennis Sylvester,et al.  Interconnect scaling: signal integrity and performance in future high-speed CMOS designs , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[6]  Eby G. Friedman,et al.  Crosstalk modeling for coupled RLC interconnects with application to shield insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Jun-Fa Mao,et al.  Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005 .

[8]  Andrew B. Kahng,et al.  Optimal equivalent circuits for interconnect delay calculations using moments , 1994, EURO-DAC '94.

[9]  Madhav P. Desai,et al.  Interconnect delay minimization using a novel pre-mid-post buffer strategy , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[10]  A. Naeemi,et al.  On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities , 2006, 2006 International Interconnect Technology Conference.

[11]  C. Paul.  Introduction to electromagnetic compatibility , 2005 .

[12]  Dimitrios Velenis,et al.  Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[13]  Xia Li,et al.  Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect , 2009, IEEE Transactions on Electron Devices.

[14]  Guoqing Chen,et al.  An RLC interconnect model based on fourier analysis , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Mohamed A. Elgamel,et al.  Efficient shield insertion for inductive noise reduction in nanometer technologies , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  N. Masoumi,et al.  Predictive Estimation for Distribution of Interconnects , 2008, 2008 12th IEEE Workshop on Signal Propagation on Interconnects.

[17]  Malgorzata Marek-Sadowska,et al.  Crosstalk reduction for VLSI , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[19]  J. Gill,et al.  High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[20]  Masud H. Chowdhury,et al.  Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Anestis Dounavis,et al.  Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Hao Yu,et al.  Staggered twisted-bundle interconnect for crosstalk and delay reduction , 2005, Sixth international symposium on quality electronic design (isqed'05).

[23]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[24]  Chauchin Su,et al.  A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[25]  Uri C. Weiser,et al.  Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.

[26]  R. Venkatesan,et al.  Impact of size effects on the resistivity of copper wires and consequently the design and performance of metal interconnect networks , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

[27]  Andrew B. Kahng,et al.  On switch factor based analysis of coupled RC interconnects , 2000, Proceedings 37th Design Automation Conference.

[28]  Rajib Kar,et al.  Wave propagation based analytical delay and cross talk noise model for distributed on-chip RLCG interconnects , 2010, 2010 IEEE International Conference on Semiconductor Electronics (ICSE2010).

[29]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[30]  F. Fiori,et al.  Worst-Case Induced Disturbances in Digital and Analog Interchip Interconnects by an External Electromagnetic Plane Wave—Part I: Modeling and Algorithm , 2011, IEEE Transactions on Electromagnetic Compatibility.