Offline error-detection strategies for the IDEA NXT crypto-algorithm

This paper presents a series of Built-In Self-Test architectures designed for the IDEA NXT family of crypto-algorithms implemented in crypto-chips. The proposed error-detection schemes are capable of verifying the integrity of the crypto-chip in an autonomous, non-concurrent manner. One of the testing solutions consists of stimulating the algorithm with test vectors generated by the IDEA NXT core while the other one stimulate the cryptographic device by means of conventional test pattern generation techniques implemented as cellular automata, linear feedback shift registers and binary counters. Both methods evaluate the outputs' correctness by means of signature analysis. The test schemes we propose offer a good trade-off between the latency of the test process and the area investment for including the error detection architectures.

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