A methodology for estimating co-scheduling slowdowns due to memory bus contention on multicore nodes

When two or more programs are co-scheduled on the same multicore computer they might experience a slowdown due to the limited off-chip memory bandwidth. According to our measurements, this slowdown ...

[1]  Alexandra Fedorova,et al.  Addressing shared resource contention in multicore processors via scheduling , 2010, ASPLOS XV.

[2]  Yan Solihin,et al.  QoS policies and architecture for cache/memory in CMP platforms , 2007, SIGMETRICS '07.

[3]  Andreas de Blanche,et al.  Method for Experimental Measurement of an Applications Memory Bus Usage , 2010, PDPTA.

[4]  Dimitrios S. Nikolopoulos,et al.  Realistic Workload Scheduling Policies for Taming the Memory Bandwidth Bottleneck of SMPs , 2004, HiPC.

[5]  Jie Chen,et al.  Analysis and approximation of optimal co-scheduling on Chip Multiprocessors , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[6]  Nectarios Koziris,et al.  Memory and network bandwidth aware scheduling of multiprogrammed workloads on clusters of SMPs , 2006, 12th International Conference on Parallel and Distributed Systems - (ICPADS'06).

[7]  Yan Solihin,et al.  Predicting inter-thread cache contention on a chip multi-processor architecture , 2005, 11th International Symposium on High-Performance Computer Architecture.

[8]  Lingjia Tang,et al.  The impact of memory subsystem resource sharing on datacenter applications , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[9]  Jack J. Dongarra,et al.  A Portable Programming Interface for Performance Evaluation on Modern Processors , 2000, Int. J. High Perform. Comput. Appl..

[10]  Pen-Chung Yew,et al.  On mitigating memory bandwidth contention through bandwidth-aware scheduling , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).