Round-off scheme for a high-speed modified Booth's algorithm multiplier

The modified Booth's algorithm multiplier is described and a round-off scheme is proposed. Based on this scheme a 12×12 bit multiplier, with the product rounded-off to 16-bits was implemented in hardware in a special purpose, high performance microprocessor, the SPP. The proposed scheme is not a strict round-off in the mathematical sense. Therefore, it is described in detail to allow a potential user to simulate the effects on his signal processing algorithm.