Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit
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[1] Davide De Caro,et al. Efficient Logarithmic Converters for Digital Signal Processing Applications , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.
[2] Tso-Bing Juang,et al. A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[3] Sunil P. Khatri,et al. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] J. Chen,et al. Enhancing parallel-prefix structures using carry-save notation , 2008, 2008 51st Midwest Symposium on Circuits and Systems.
[5] ERNEST L. HALL,et al. Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications , 1970, IEEE Transactions on Computers.
[6] Hao-Yung Lo,et al. A Hardwired Generalized Algorithm for Generating the Logarithm Base-k by Iteration , 1987, IEEE Transactions on Computers.
[7] Jun Chen. Parallel -prefix structures for binary and modulo {2n -- 1, 2n, 2n + 1} adders , 2008 .
[8] Arnaud Tisserand,et al. Multipartite table methods , 2005, IEEE Transactions on Computers.
[9] Michael J. Schulte,et al. The Symmetric Table Addition Method for Accurate Function Approximation , 1999, J. VLSI Signal Process..
[10] Chip-Hong Chang,et al. A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] Kaushik Roy,et al. Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] Bruce F. Cockburn,et al. A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions , 2010, IEEE Transactions on Computers.
[13] Haridimos T. Vergos,et al. Diminished-One Modulo 2n+1 Adder Design , 2002, IEEE Trans. Computers.
[14] Ching-Chuen Jong,et al. A Memory-Efficient Tables-and-Additions Method for Accurate Computation of Elementary Functions , 2013, IEEE Transactions on Computers.
[15] Yang Jing,et al. FPGA Design and Implementation of an Improved 32-bit Binary Logarithm Converter , 2008, 2008 4th International Conference on Wireless Communications, Networking and Mobile Computing.
[16] Hoi-Jun Yoo,et al. Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems , 2008, IEEE Transactions on Computers.
[17] Y. Mukaigawa,et al. Large Deviations Estimates for Some Non-local Equations I. Fast Decaying Kernels and Explicit Bounds , 2022 .
[18] T VergosHaridimos,et al. Diminished-One Modulo 2^n +1 Adder Design , 2002 .
[19] Shen-Fu Hsiao,et al. An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[20] Peng Huang,et al. Convergence Analysis of Jacobi Iterative Method Using Logarithmic Number System , 2008, Seventh IEEE/ACIS International Conference on Computer and Information Science (icis 2008).
[21] K. Sridharan,et al. 50 Years of CORDIC: Algorithms, Architectures, and Applications , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[22] Peter Lee. An evaluation of a hybrid-logarithmic number system DCT/IDCT algorithm [image compression applications] , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[23] J. C. Majithia,et al. A note on base-2 logarithm computations , 1973 .
[24] D. De Caro,et al. A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 $\mu\hbox{m}$ CMOS , 2008, IEEE Journal of Solid-State Circuits.
[25] Jack E. Volder. The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..
[26] Vassilis Paliouras,et al. Considering the alternatives in low-power design , 2001 .
[27] Sanu Mathew,et al. A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS , 2013, IEEE Journal of Solid-State Circuits.
[28] Khalid H. Abed,et al. CMOS VLSI Implementation of a Low-Power Logarithmic Converter , 2003, IEEE Trans. Computers.
[29] Sanu Mathew,et al. A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[30] E. V. Krishnamurthy,et al. On Computer Multiplication and Division Using Binary Logarithms , 1963, IEEE Transactions on Electronic Computers.
[31] Davide De Caro,et al. Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations , 2011, IEEE Transactions on Computers.
[32] Hoi-Jun Yoo,et al. A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System , 2005, IEEE Journal of Solid-State Circuits.
[33] M. Combet,et al. Computation of the Base Two Logarithm of Binary Numbers , 1965, IEEE Trans. Electron. Comput..
[34] Javier Valls-Coquillat,et al. Low Cost Hardware Implementation of Logarithm Approximation , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[35] S. L. SanGregory,et al. A fast, low-power logarithm approximation with CMOS VLSI implementation , 1999, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356).
[36] Sanjeev Saxena,et al. On Parallel Prefix Computation , 1994, Parallel Process. Lett..
[37] Earl E. Swartzlander,et al. Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations , 2010, IEEE Transactions on Computers.
[38] Michael J. Schulte,et al. Approximating Elementary Functions with Symmetric Bipartite Tables , 1999, IEEE Trans. Computers.