Electrical validation of through process OPC verification limits
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Edward W. Conrad | James A. Bruce | Omprakash Jaiswal | Rakesh Kuncha | Taksh Bharat | Vipin Madangarli | Sajan Marokkey
[1] James A. Bruce,et al. Predicting yield using model based OPC verification: calibrated with electrical test data , 2008, SPIE Advanced Lithography.
[2] Dragos Dudau,et al. Dense OPC and verification for 45nm , 2006, SPIE Advanced Lithography.
[3] Edward W. Conrad,et al. Model-based verification for first time right manufacturing , 2005, SPIE Advanced Lithography.
[4] M. Hall,et al. A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software , 2006, 2006 IEEE International Conference on Microelectronic Test Structures.