Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations

A power-consumption-centric assignment algorithm called partially fixed configuration mapping (PFCM) is proposed for multi-context dynamically reconfigurable processors. By assigning the same operations into the same PE (processing element) as many as possible, the amount of changing configuration data for dynamic reconfiguration can be reduced, resulting in the redundant power consumed for changing the configuration also being reduced. The proposed algorithm was implemented in a compiler for a dynamically reconfigurable processor for research. Evaluation results showed that the consumed power was reduced by 10% on average without increasing the execution time.

[1]  Rudy Lauwereins,et al.  DRESC: a retargetable compiler for coarse-grained reconfigurable architectures , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[2]  Hideharu Amano,et al.  Black-Diamond : a Retargetable Compiler using Graph with Configuration Bits for Dynamically Reconfigurable Architectures , 2008 .

[3]  Takashi Nishimura,et al.  Power reduction techniques for Dynamically Reconfigurable Processor Arrays , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[4]  Jie S. Hu,et al.  Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors , 2007, ERSA.

[5]  Hideharu Amano,et al.  Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[6]  Dan Grossman,et al.  Macah: A "C-Level" Language for Programming Kernels on Coprocessor Accelerators , 2008 .

[7]  Hideharu Amano,et al.  Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction , 2011, ARC.

[8]  Hideharu Amano,et al.  RoMultiC: fast and simple configuration data multicasting scheme for coarse grain reconfigurable devices , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[9]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Takashi Nishimura,et al.  Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique , 2008, 2008 International Conference on Field-Programmable Technology.

[11]  Kiyoung Choi,et al.  Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Li Jing,et al.  High-Level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[13]  Hideharu Amano,et al.  MuCCRA-3: A low power dynamically Reconfigurable Processor Array , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[14]  Hideharu Amano,et al.  Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells , 2009, 2009 International Conference on Field-Programmable Technology.