Semiconductor memory device providing analiysis and relief of soft data fail in stacked chips

The semiconductor memory device of the present invention provides a fail-soft data analysis and relief features in stacked chip structure. The semiconductor memory device described in claim 2 including a first group of die, a plurality of memory dies communicating data via said first and stacked on top of one group of Die plurality of through-line with the at least one buffer die and a group of dies. At least one of the plurality of memory dies has a first type ECC circuit for generating the parity bit transmitted with the transmission data transmitted to the first group of Die. In addition, the buffer die is the second type ECC to generate error-corrected data by as correcting the transmission error using the transmitted parity bit in the case of a transmission error in the transmission data received via the plurality of through-line generation It has the circuit.