To further improve the characteristics of CMOS image sensors (CIS), we propose a back-side illuminated pixel integrating a vertically pinned and P-type photodiode (which collects holes) and PMOS readout circuitry. It has been designed in a 1.4μm-pitch, a two-transistor (2T) shared readout architecture and fabricated in a combined 65nm and 90nm technology. The vertically pinned photodiode takes up almost the entire volume of the pixel, allowing a full well capacity (FWC) exceeding 7000h+. With a conversion factor around 120μV/h+, the output swing approaching 1V is achieved on the column voltage. The pixel also integrates capacitive deep trench isolation (CDTI) to tackle electrical and optical crosstalk issues. The effective passivation of trench interface by CDTI bias control is demonstrated for a hole-based pixel. As expected, PMOS transistors have much lower trapping noise compared to NMOS counterparts. The PMOS source follower has an average temporal noise of 195μV, mainly dominated by thermal noise contribution.
[1]
Francois Roy,et al.
Back Illuminated Vertically Pinned Photodiode with in Depth Charge Storage
,
2011
.
[2]
Eric G. Stevens,et al.
Low-Crosstalk and Low-Dark-Current CMOS Image-Sensor Technology Using a Hole-Based Detector
,
2008,
2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[3]
F. Roy,et al.
Rad Tolerant CMOS Image Sensor Based on Hole Collection 4T Pixel Pinned Photodiode
,
2012,
IEEE Transactions on Nuclear Science.
[4]
F. Leverd,et al.
MOS Capacitor Deep Trench Isolation for CMOS image sensors
,
2014,
2014 IEEE International Electron Devices Meeting.