A merged CMOS/bipolar VLSI process

Presented are the results of a merged CMOS/bipolar process used to implement circuit structures using both fully isolated bipolar transistors with low collector series resistance and CMOS transistors. Latch-up suppression and effective bipolar performance are simultaneously achieved by the combined use of an n+ buried layer, epitaxial processing and a tailored base ion implant. A merged CMOS/bipolar buffer circuit is described and measured results are shown.

[1]  M. Kubo,et al.  A high-speed, low-power Hi-CMOS 4K static RAM , 1978, 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  A. Ochoa,et al.  Latch-Up Control in CMOS Integrated Circuits , 1979, IEEE Transactions on Nuclear Science.

[3]  R.D. Rung,et al.  A retrograde p-well for higher density CMOS , 1981, IEEE Transactions on Electron Devices.

[4]  High-density and reduced latchup susceptibility CMOS technology for VLSI , 1983, IEEE Electron Device Letters.