An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

A small-size inductive-coupling dc voltage transceiver for highly-parallel wafer-level testing is experimentally demonstrated in 90-nm CMOS technology, which can reduce the total cost of a low-price IC by 18%. In order to carry out dc tests, the proposed transceiver outputs dc voltage to the die-under-test (DUT) without any area-consuming digital circuits. In addition, digital calibration with digital feedback channel which calibrates the output dc voltage enables the removal of calibration circuits on the DUT. All of the circuits for dc tests are implemented into the area of an inductor (100 μm ×100 μm). The proposed dc voltage transmission is successfully demonstrated with 6-bit resolution.

[1]  M.S.J. Steyaert,et al.  A 10-bit 250-MS/s binary-weighted current-steering DAC , 2004, IEEE Journal of Solid-State Circuits.

[2]  Lin Fu,et al.  Noncontact wafer probe using wireless probe cards , 2005, IEEE International Conference on Test, 2005..

[3]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[4]  Yasuhiro Morita,et al.  Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Tadahiro Kuroda,et al.  An 11Gb/s Inductive-Coupling Link with Burst Transmission , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Y. Yoshida,et al.  A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array , 2007, IEEE Journal of Solid-State Circuits.

[7]  Michel Renovell,et al.  System-in-Package, a Combination of Challenges and Solutions , 2007, 12th IEEE European Test Symposium (ETS'07).

[8]  T. Sakurai,et al.  A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[9]  W. R. Mann,et al.  The leading edge of production wafer probe test technology , 2004 .

[10]  T. Sakurai,et al.  A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link , 2007, IEEE Journal of Solid-State Circuits.

[11]  T. Sakurai,et al.  Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array , 2007, IEEE Journal of Solid-State Circuits.

[12]  M. Takamiya,et al.  A sampling oscilloscope macro toward feedback physical design methodology , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).