Testing in the Direct Mapping Domain *

The application of asynchronous circuits has been restricted because of the lack of technology to test them. In this paper we introduce a technique to test circuits obtained by the direct mapping technique from 1-safe Petri nets. Low-level physical faults in the cells implementing Petri net places are analysed and mapped into the high-level specification, a Petri net. This technique uses a “pseudo clock” in order to handle the hazards which may occur under certain types of physical faults. The clock also helps to activate faults which exhibit themselves only under some particular arrangement of signals and to deliver the precise information about the fault location to the test point.

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