An automatic evaluation of phase noise on CMOS ring VCOs

The presence of phase noise in semiconductor devices can disturb the normal operation of analog and RF circuits. This paper presents a methodology to automatically evaluate the effects of phase noise in ring voltage controlled oscillators (VCOs). The methodology is based on SPICE circuit simulations and a mathematical analysis. A CAD tool was implemented and used to evaluate and optimize a four-stage ring VCO to show the effectiveness of the methodology