Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication

In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18-mum CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER<10-14. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width

[1]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[2]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[3]  D. J. Allstot,et al.  A 0.5-8.5 GHz fully differential CMOS distributed amplifier , 2002 .

[4]  J.G. Linvill,et al.  Transistor Negative-Impedance Converters , 1953, Proceedings of the IRE.

[5]  B. Razavi,et al.  10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology , 2003, IEEE J. Solid State Circuits.

[6]  W.J. Dally,et al.  Low-power area-efficient high-speed I/O circuit techniques , 2000, IEEE Journal of Solid-State Circuits.

[7]  G. Patounakis,et al.  Pulsed current-mode signaling for nearly speed-of-light intrachip communication , 2006, IEEE Journal of Solid-State Circuits.

[8]  Frank O'Mahony,et al.  A 10-GHz global clock distribution using coupled standing-wave oscillators , 2003 .

[9]  Changkyu Kim,et al.  Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches , 2003, IEEE Micro.

[10]  K.L. Shepard,et al.  Distributed Loss Compensation for Low-latency On-chip Interconnects , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[11]  Behzad Razavi.  A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs , 1999 .

[12]  Richard T. Witek,et al.  A 160 MHz 32 b 0.5 W CMOS RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[13]  Noel Menezes,et al.  Repeater scaling and its impact on CAD , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Jaeha Kim,et al.  Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..