Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading

Pairs trading is a solidly profitable strategy in the algorithmic trading area, and an important step of this strategy is selecting pairs of stocks. Compared with other existing pairs selection approaches, the Engle-Granger cointegration is more stable and reliable. Nowadays, as trading is becoming faster and faster in stock markets all over the world, it is necessary to accelerate the pairs selection process to increase potential profits. However, intensive computations and complicated data flow in the cointegration approach bring challenges to hardware acceleration. In this paper, for the first time, we propose an efficient and hardware-friendly computing scheme to accelerate the Engle-Granger cointegration. Besides, a novel algorithmic strength reduction strategy and approximation methods are used to significantly reduce the complexity of the proposed scheme. Based on the improved algorithm, both FPGA and ASIC accelerators are developed. The implementation results show that our FPGA and ASIC accelerators perform <inline-formula> <tex-math notation="LaTeX">$36\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$207\times $ </tex-math></inline-formula> faster than GPU, respectively. Thus, our design can significantly reduce the latency of the pairs selection process, and make more profit for investors and traders.

[1]  Song Han,et al.  EIE: Efficient Inference Engine on Compressed Deep Neural Network , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[2]  H. Akaike,et al.  Information Theory and an Extension of the Maximum Likelihood Principle , 1973 .

[3]  William N. Goetzmann,et al.  Pairs Trading: Performance of a Relative Value Arbitrage Rule , 1998 .

[4]  W. P. Malcolm,et al.  Pairs trading , 2005 .

[5]  Pei-Yun Tsai,et al.  Efficient Implementation of QR Decomposition for Gigabit MIMO-OFDM Systems , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Jiayu Wu,et al.  A Pairs Trading Strategy for GOOG/GOOGL Using Machine Learning , 2015 .

[7]  C. Granger,et al.  Co-integration and error correction: representation, estimation and testing , 1987 .

[8]  Xun Xu,et al.  A good pair: alternative pairs-trading strategies , 2017 .

[9]  Song-Ping Zhu,et al.  Optimal investment and consumption under a continuous-time cointegration model with exponential utility , 2019, Quantitative Finance.

[10]  Hossein Rad,et al.  The Profitability of Pairs Trading Strategies: Distance, Cointegration, and Copula Methods , 2015 .

[11]  W. Li,et al.  A single-stage approach for cointegration-based pairs trading , 2017, Finance Research Letters.

[12]  Chiao-En Chen,et al.  A Systolic Array Based GTD Processor With a Parallel Algorithm , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Nicolas Huck,et al.  Pairs trading and selection methods: is cointegration superior? , 2015 .

[14]  G. Vidyamurthy.  Pairs Trading: Quantitative Methods and Analysis , 2004 .

[15]  Matthew Baron,et al.  Risk and Return in High-Frequency Trading , 2017, Journal of Financial and Quantitative Analysis.

[16]  M. H. Mickle,et al.  Three-dimensional computational pipelining with minimal latency and maximum throughput for L-U factorization , 1998 .

[17]  Franck Martin,et al.  Pairs trading strategies in a cointegration framework: back-tested on CFD and optimized by profit factor , 2018, Applied Economics.

[18]  Bao Rong Chang,et al.  An Intelligent Model for Pairs Trading Using Genetic Algorithms , 2015, Comput. Intell. Neurosci..

[19]  A. Tourin,et al.  Model-based pairs trading in the bitcoin markets , 2017 .

[20]  Matthew Clegg,et al.  Pairs trading with partial cointegration , 2018 .

[21]  M. Omair Ahmad,et al.  FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[22]  Junzhong Shen,et al.  Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[23]  Yasuaki Inoue,et al.  High-performance systolic arrays for band matrix multiplication , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[24]  Siyuan Lu,et al.  Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading , 2020, ISCAS.

[25]  Keshab K. Parhi,et al.  A novel systolic array structure for DCT , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[26]  Gopal Rao Madhavaram.  Statistical arbitrage using pairs trading with support vector machine learning , 2013 .

[27]  Oscar Gustafsson,et al.  Hardware architecture for positive definite matrix inversion based on LDL decomposition and back-substitution , 2016, 2016 50th Asilomar Conference on Signals, Systems and Computers.