Built-in test of CMOS state machines with realistic faults: a system perspective

The design of built-in test systems for large arrays is approached from the viewpoint of detecting real faults in the mask layers of a typical CMOS process. The resulting testable design and built-in test system provides a practical compromise between the costly hardware augmentation plaguing existing techniques and circuit independence of the test procedure. Built-in testability is achieved independently of feedback. Therefore, combinational and sequential circuits can be tested in parallel with exactly the same hardware and method. The test-specific hardware overhead decreases rapidly with increasing circuit size and falls below 10% for large arrays with more than 100 product terms. No additional gate delays are introduced into the critical path by the test circuitry. The normal circuit performance is, therefore, left intact with the exception of a minimal degradation associated with adding tristate capability to the input buffers. >

[1]  Kozo Kinoshita,et al.  A Design of Programmable Logic Arrays with Universal Tests , 1981, IEEE Transactions on Computers.

[2]  Mani Soma,et al.  A BIST design of structured arrays with fault-tolerant layout , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[3]  A. V. Ferris-Prabhu,et al.  Defect size variations and their effect on the critical area of VLSI devices , 1985 .

[4]  Hideo Fujiwara,et al.  A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead , 1987, IEEE Transactions on Computers.

[5]  Kozo Kinoshita,et al.  Design of Diagnosable Sequential Machines Utilizing Extra Outputs , 1974, IEEE Transactions on Computers.

[6]  Asok Bhattacharyya.  On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs , 1983, IEEE Transactions on Computers.

[7]  Emile H. L. Aarts,et al.  Design-for-Testability of PLA'S Using Statistical Cooling , 1986, DAC 1986.

[8]  Kewal K. Saluja,et al.  An Alternative to Scan Design Methods for Sequential Machines , 1986, IEEE Transactions on Computers.

[9]  Edward J. McCluskey,et al.  Concurrent Error Detection and Testing for Large PLA's , 1982 .

[10]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[11]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Mani Soma,et al.  Built-in test of CMOS state machines with realistic faults: a system perspective , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[13]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[14]  Edward J. McCluskey,et al.  Lower Overhead Design for Testability of Programmable Logic Arrays , 1986, IEEE Transactions on Computers.

[15]  Andrzej J. Strojwas,et al.  VLSI Yield Prediction and Estimation: A Unified Framework , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Dhiraj K. Pradhan.  Sequential Network Design Using Extra Inputs for Fault Detection , 1983, IEEE Transactions on Computers.

[17]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[18]  Kozo Kinoshita,et al.  Easily Testable Sequential Machines with Extra Inputs , 1975, IEEE Transactions on Computers.

[19]  D. F. Wong,et al.  PLA folding by simulated annealing , 1987 .

[20]  Kozo Kinoshita,et al.  An Easily Testable Design of Programmable Logic Arrays for Multiple Faults , 1983, IEEE Transactions on Computers.

[21]  Mani Soma,et al.  Practical built-in test of CMOS state machines with realistic faults , 1989, IEEE International Symposium on Circuits and Systems,.

[22]  W. Daehn,et al.  A hardware approach to self-testing of large programmable logic arrays , 1981 .

[23]  Syed Zahoor Hassan.  An Efficient Self-Test Structure for Sequential Machines , 1986, ITC.