Effects of Cache Coherency in Multiprocessors

In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which prevents the existence of several different copies of the same data block in different private caches. In this paper, we present an in-depth analysis of the effects of cache coherency in multiprocessors. A novel analytical model for the program behavior of a multitasked system is introduced. The model includes the behavior of each process and the interactions between processes with regard to the sharing of data blocks. An approximation is developed to derive the main effects of the cache coherency contributing to degradations in system performance.

[1]  Edward S. Davidson,et al.  Organization of Semiconductor Memories for Parallel-Pipelined Processors , 1977, IEEE Transactions on Computers.

[2]  Gordon Bell,et al.  An Investigation of Alternative Cache Organizations , 1974, IEEE Transactions on Computers.

[3]  Chi-Chung Yeh Shared Cache Organization for Multiple-Stream Computer Systems , 1981 .

[4]  Jeffrey R. Spirn,et al.  Program Behavior: Models and Measurements , 1977 .

[5]  Robert O. Winder,et al.  Cache-based Computer Systems , 1973, Computer.

[6]  Jerome H. Saltzer,et al.  A simple linear model of demand paging performance , 1974, Commun. ACM.

[7]  Michel Dubois,et al.  Efficient interprocessor communication for MIMD multiprocessor systems , 1981, ISCA '81.

[8]  H. T. Kung The Structure of Parallel Algorithms , 1980, Adv. Comput..

[9]  Michel Dubois ANALYTICAL METHODOLOGIES FOR THE EVALUATION OF MULTIPROCESSING STRUCTURES , 1982 .

[10]  Calvin K. Tang Cache system design in the tightly coupled multiprocessor system , 1976, AFIPS '76.

[11]  Jacques Leroudier,et al.  Performance Evaluation of a Cache Memory for a Mini-computer , 1979, Performance.

[12]  Paul Feautrier,et al.  A New Solution to Coherence Problems in Multicache Systems , 1978, IEEE Transactions on Computers.

[13]  Wei-Chen Yen MEMORY ORGANIZATION AND SYNCHRONIZATION MECHANISM OF MULTIPROCESSING COMPUTER SYSTEMS , 1981 .

[14]  William D. Strecker Cache memories for PDP-11 family computers , 1976, ISCA.

[15]  Peter J. Denning,et al.  Working Sets Past and Present , 1980, IEEE Transactions on Software Engineering.

[16]  Mahadev Satyanarayanan Special Feature: Commercial Multiprocessing Systems , 1980, Computer.

[17]  Michel Dubois,et al.  Performance of cache-based multiprocessors , 1981, SIGMETRICS '81.