Economic and productivity considerations in ASIC test and design-for-test

The results of a test and DFT (design-for-test) productivity study are presented. A questionnaire consisting of over 30 questions was distributed to design engineers. From the 30 responses received, predictive models were developed for important areas of test and DFT. Using these models the life-cycle cost of a product can be estimated before the project is undertaken. The models can also be used to select methodologies and techniques that will put the project at the economic test point. The models are used to evaluate various strategies for implementing an ASIC (application-specific integrated circuit) product optimizing its total life-cycle cost. The estimates that are performed can be used in the product planning phase to help make decisions about such factors as design styles, DFT approaches, manpower, and schedules so that market commitments are satisfied in the most cost-effective manner.<<ETX>>