A DFE equalizer ASIC chip using the MMA algorithm

This paper proposes an equalizer using MMA (Multi-Modulus Algorithm) and LMS (Least Mean Square) algorithms and uses a DFE (Decision Feedback Equalizer) structure. The existing MMA equalizer uses two transversal filters but the proposed equalizer uses two DFE filter banks to improve the channel adaptive performance and to reduce the number of taps. The fabricated equalizer ASIC chip using MMA and LMS algorithms operates at 8 MHz and provides 64 Mbps which is higher than existing equalizers. The chip uses the 0.35 /spl mu/m technology and has about 160,000 gates.

[1]  D. W. Lin,et al.  Joint low-complexity blind equalization, carrier recovery, and timing recovery with application to cable modem transmission , 1999 .

[2]  D. W. Lin,et al.  An efficient FSE/DFE-based HDSL equalizer with new adaptive algorithms , 1994, Proceedings of ICC/SUPERCOMM'94 - 1994 International Conference on Communications.

[3]  Hyeonseok Hwang,et al.  Adaptive blind equalization coupled with carrier recovery for HDTV modem , 1993 .

[4]  Behrouz Farhang-Boroujeny,et al.  Design of multilevel decision feedback equalizers , 1997 .

[5]  Guy A. Dumont,et al.  The multimodulus blind equalization algorithm , 1997, Proceedings of 13th International Conference on Digital Signal Processing.

[6]  H. Samueli,et al.  A 70 Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10 b ADC and FEC decoder , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).