BabelFish: Fusing Address Translations for Containers

Cloud computing has begun a transformation from using virtual machines to containers. Containers are attractive because multiple of them can share a single kernel, and add minimal performance overhead. Cloud providers leverage the lean nature of containers to run hundreds of them on a few cores. Furthermore, containers enable the serverless paradigm, which leads to the creation of short-lived processes.In this work, we identify that containerized environments create page translations that are extensively replicated across containers in the TLB and in page tables. The result is high TLB pressure and redundant kernel work during page table management. To remedy this situation, this paper proposes BabelFish, a novel architecture to share page translations across containers in the TLB and in page tables. We evaluate BabelFish with simulations of an 8-core processor running a set of Docker containers in an environment with conservative container co-location. On average, under BabelFish, 53% of the translations in containerized workloads and 93% of the translations in serverless workloads are shared. As a result, BabelFish reduces the mean and tail latency of containerized data-serving workloads by 11% and 18%, respectively. It also lowers the execution time of containerized compute workloads by 11%. Finally, it reduces serverless function bring-up time by 8% and execution time by 10%–55%.

[1]  Ján Veselý,et al.  Hardware translation coherence for virtualized systems , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[2]  Adam Silberstein,et al.  Benchmarking cloud serving systems with YCSB , 2010, SoCC '10.

[3]  Abhishek Bhattacharjee,et al.  Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces , 2014, ASPLOS.

[4]  Alan L. Cox,et al.  Shared address translation revisited , 2016, EuroSys.

[5]  Roy T. Fielding,et al.  The Apache HTTP Server Project , 1997, IEEE Internet Comput..

[6]  Abhishek Bhattacharjee,et al.  Efficient Address Translation for Architectures with Multiple Page Sizes , 2017, ASPLOS.

[7]  Margaret Martonosi,et al.  Shared last-level TLBs for chip multiprocessors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

[8]  Neil Savage,et al.  Going serverless , 2018, Commun. ACM.

[9]  K. Gopinath,et al.  Making Huge Pages Actually Useful , 2018, ASPLOS.

[10]  Lucas Chaufournier,et al.  Containers and Virtual Machines at Scale: A Comparative Study , 2016, Middleware.

[11]  Yan Solihin,et al.  Scheduling Page Table Walks for Irregular GPU Applications , 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

[12]  Guy E. Blelloch,et al.  GraphChi: Large-Scale Graph Computation on Just a PC , 2012, OSDI.

[13]  Jure Leskovec,et al.  {SNAP Datasets}: {Stanford} Large Network Dataset Collection , 2014 .

[14]  Bruce Jacob,et al.  The structural simulation toolkit , 2006, PERV.

[15]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[16]  Boris Grot,et al.  Prefetched Address Translation , 2019, MICRO.

[17]  Wenzhi Cui,et al.  Simulation and Analysis Engine for Scale-Out Workloads , 2016, ICS.

[18]  Nadav Amit,et al.  Optimizing the TLB Shootdown Algorithm with Page Access Tracking , 2017, USENIX Annual Technical Conference.

[19]  Josep Torrellas,et al.  Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism , 2020, ASPLOS.

[20]  Krste Asanovic,et al.  Mondrian memory protection , 2002, ASPLOS X.

[21]  Youngjin Kwon,et al.  Coordinated and Efficient Huge Page Management with Ingens , 2016, OSDI.

[22]  Michael M. Swift,et al.  Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[23]  Lizy Kurian John,et al.  CSALT: Context Switch Aware Large TLB* , 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[24]  Jiwon Kim,et al.  Efficient Memory Mapped File I/O for In-Memory File Systems , 2017, HotStorage.

[25]  Timothy C. Bell,et al.  Selecting a hashing algorithm , 1990, Softw. Pract. Exp..

[26]  Bruce Jacob,et al.  DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.

[27]  Jee Ho Ryoo,et al.  Rethinking TLB designs in virtualized environments: A very large part-of-memory TLB , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[28]  David Wentzlaff,et al.  Architectural Implications of Function-as-a-Service Computing , 2019, MICRO.

[29]  Christina Delimitrou,et al.  X-Containers: Breaking Down Barriers to Improve Performance and Isolation of Cloud-Native Containers , 2019, ASPLOS.

[30]  Amro Awad,et al.  Samba: A Detailed Memory Management Unit (MMU) for the SST Simulation Framework , 2016 .

[31]  Aamer Jaleel,et al.  CoLT: Coalesced Large-Reach TLBs , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[32]  Gabriel H. Loh,et al.  Increasing TLB reach by exploiting clustering in page translations , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

[33]  Brendan Burns,et al.  Design Patterns for Container-based Distributed Systems , 2016, HotCloud.

[34]  Tianhao Zhang,et al.  Do-it-yourself virtual memory translation , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

[35]  Osman S. Unsal,et al.  Redundant Memory Mappings for fast access to large memories , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[36]  Yan Solihin,et al.  Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries , 2017, 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT).

[37]  Christoforos E. Kozyrakis,et al.  Pocket: Elastic Ephemeral Storage for Serverless Analytics , 2018, OSDI.

[38]  Mohan Kumar,et al.  LATR: Lazy Translation Coherence , 2018, ASPLOS.

[39]  Yousef A. Khalidi,et al.  Improving the Address Translation Performance of Widely Shared Pages , 1995 .

[40]  Josep Torrellas,et al.  PageForge: A Near-Memory Content-Aware Page-Merging Architecture , 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).