A motor speed control system using dual-loop PLL and speed feed-forward/back

PLL speed control systems can completely reject speed error and steady-state phase error for constant-speed inputs. Though it does not usually handle inputs including acceleration, the dual-loop scheme improves, as a feed-forward control system, rising time and phase error for acceleration input. However, since it is fundamentally a third-order PLL, it has slow rising up characteristics than speed feed-back, and cannot avoid over/undershoots. Nonetheless, the first loop has rapid rising up characteristics and no over/undershoot, since it is an ideal second-order PLL system. In this article, to solve the problem, we show a hybrid system of the dual-loop PLL and speed feed-forward/back. It has fast rising up characteristics and no over/undershoots thanks to the first and third PLL as F/V converter, which cannot be achieved in traditional PLL systems.

[1]  Chung-Yuen Won,et al.  PLL control algorithm for precise speed control of the slotless PM brushless DC motor Using 2 Hall-ICs , 2004, 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551).

[2]  Iwao Sasase,et al.  Third-order phase-locked loops using dual loops inserting an active filter in the second loop with improved stability , 2001 .

[3]  Fuminori Kobayashi,et al.  A motor speed control system using a hybrid of dual-loop PLL and feed-forward , 2010, 2010 11th IEEE International Workshop on Advanced Motion Control (AMC).

[4]  A. W. Moore,et al.  Phase-locked loops for motor-speed control , 1973, IEEE Spectrum.

[5]  J. X. Shen,et al.  Sensorless control of ultrahigh-speed PM brushless motor using PLL and third harmonic back EMF , 2006, IEEE Transactions on Industrial Electronics.

[6]  Fuminori Kobayashi,et al.  A PWM motor speed control system based on the dual-loop PLL , 2009, 2009 ICCAS-SICE.

[7]  Ching-Tsai Pan,et al.  A Phase-Locked-Loop-Assisted Internal Model Adjustable-Speed Controller for BLDC Motors , 2008, IEEE Transactions on Industrial Electronics.

[8]  J. Deskur,et al.  Application of digital phase locked loop for control of SRM drive , 2007, 2007 European Conference on Power Electronics and Applications.