Inter-layer vias and TESH interconnection network for a 3-D heterogeneous sensor system on a chip

In a previous paper we had described a novel concept on ultra-small, ultra-compact, unattended multi-phenomenological sensor systems for rapid deployment, with integrated classification-and-decision-information extraction capability from the sensed environment. Specifically, we had proposed placing such integrated capability on a 3-D Heterogeneous System on a Chip (HSoC). This paper amplifies two key aspects of that future sensor technology. These are the creation of inter-layer vias by high aspect ratio MPS (Macro Porous Silicon) process, and the adaptation of the TESH (Tori connected mESHes) network to bind the diverse leaf nodes on multiple layers of the 3-D structure. Interesting also is the inter-relationship between these two aspects. In particular, the issue of overcoming via failures, catastrophic as well as high-resistance failures, through the existence of alternative paths in the TESH network and corresponding routing strategies is discussed. A probabilistic model for via failures is proposed and the testing of the vias between the sensor layer and the adjacent processing layer is discussed.

[1]  Glenn H. Chapman,et al.  Defect avoidance in a 3-D heterogeneous sensor [acoustic/seismic/active pixel/IR imaging sensor array] , 2004 .

[2]  Susumu Horiguchi,et al.  TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing , 1997 .

[3]  R. H. Havemann,et al.  High-performance interconnects: an integration overview , 2001, Proc. IEEE.

[4]  Glenn H. Chapman,et al.  A parallel architecture for the ICA algorithm: DSP plane of a 3-D heterogeneous sensor , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

[5]  Jang-Kyo Kim,et al.  Three-dimensional packaging for multi-chip module with through-the-silicon via hole , 2003, Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003).

[6]  Glenn H. Chapman,et al.  Level-hybrid optoelectronic TESH interconnection network , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[7]  M. Topper,et al.  New wafer-level-packaging technology using silicon-via-contacts for optical and other sensor applications , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[8]  Volker Lehmann,et al.  Porous silicon-a new material for MEMS , 1996, Proceedings of Ninth International Workshop on Micro Electromechanical Systems.

[9]  P. Arunasalam,et al.  Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[10]  J. Scholvin,et al.  A through-wafer interconnect in silicon for RFICs , 2004, IEEE Transactions on Electron Devices.

[11]  Vijay K. Jain,et al.  Automatic Reconfiguration and Yield of the TESH Multicomputer Network , 2002, IEEE Trans. Computers.

[12]  Glenn H. Chapman,et al.  Defect avoidance in a 3-D heterogeneous sensor [acoustic/seismic/active pixel/IR imaging sensor array] , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

[13]  H. Schellevis,et al.  High aspect ratio through-wafer interconnections for 3D-microsystems , 2003, The Sixteenth Annual International Conference on Micro Electro Mechanical Systems, 2003. MEMS-03 Kyoto. IEEE.

[14]  Dennis Sylvester,et al.  Impact of small process geometries on microarchitectures in systems on a chip , 2001 .

[15]  Vijay K. Jain,et al.  VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Glenn H. Chapman,et al.  3D heterogeneous sensor system on a chip for defense and security applications , 2004, SPIE Defense + Commercial Sensing.