Evolutionary strategies and intrinsic fault tolerance

Redundancy is a critical component to the design of fault tolerant systems; both hardware and software. This paper explores the possibilities of using evolutionary techniques to first produce a processing system that will perform a required function, and then consider its applicability for producing useful redundancy that can be made use of in the presence of faults, ie is it fault tolerant? Results obtained using evolutionary strategies to automatically create redundancy as part of the "design" process are given. The experiments are undertaken on a Virtex FPGA with intrinsic evolution taking place. The results show that not only does the evolutionary process produce useful redundancy, it is also possible to reconfigure the system in real-time on the Virtex device.

[1]  Gianluca Tempesti,et al.  Towards Robust Integrated Circuits: The Embryonics Approach. Proc IEEE , 2000 .

[2]  Cauligi S. Raghavendra,et al.  Gracefully Degradable Processor Arrays , 1985, IEEE Transactions on Computers.

[3]  Isamu Kajitani,et al.  Hardware Evolution at Function Level , 1996, PPSN.

[4]  Paul J. Layzell,et al.  Understanding Inherent Qualities of Evolved Circuits: Evolutionary History as a Predictor of Fault Tolerance , 2000, ICES.

[5]  Algirdas Avizienis,et al.  Fault Tolerance by Design Diversity: Concepts and Experiments , 1984, Computer.

[6]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[7]  Xin Yao,et al.  Promises and Challenges of Evolvable Hardware , 1996, ICES.

[8]  Adrian Thompson,et al.  Evolutionary techniques for fault tolerance , 1996 .

[9]  Shantanu Dutt,et al.  Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance , 1997, IEEE Trans. Computers.

[10]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[11]  Steven A. Guccione,et al.  GeneticFPGA: evolving stable circuits on mainstream FPGA devices , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[12]  Adrian Thompson.  Evolving fault tolerant systems , 1995 .

[13]  Julian Francis Miller,et al.  Evolution of Digital Filters Using a Gate Array Model , 1999, EvoWorkshops.

[14]  Andrew M. Tyrrell,et al.  Safe intrinsic evolution of Virtex devices , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[15]  Andrew M. Tyrrell,et al.  The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic , 2000, ICES.

[16]  John H. Holland,et al.  Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence , 1992 .

[17]  José A. B. Fortes,et al.  A taxonomy of reconfiguration techniques for fault-tolerant processor arrays , 1990, Computer.