A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications
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Anh-Tuan Do | Chun Kit Lam | Yung Sern Tan | Kiat Seng Yeo | Jia Hao Cheong | Lei Yao | Minkyu Je | Kuang-Wei Cheng | Xiaodan Zou
[1] Yonghwan Kim,et al. A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array , 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.
[2] Hong-June Park,et al. A 1.3μW 0.6V 8.7-ENOB successive approximation ADC in a 0.18μm CMOS , 2009, 2009 Symposium on VLSI Circuits.
[3] Hiroki Ishikuro,et al. A power scalable SAR-ADC in 0.18µm-CMOS with 0.5V nano-watt operation , 2011, 2011 1st International Symposium on Access Spaces (ISAS).
[4] Teresa H. Y. Meng,et al. Adaptive Resolution ADC Array for an Implantable Neural Sensor , 2011, IEEE Transactions on Biomedical Circuits and Systems.
[5] Ameya Bhide,et al. A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).
[6] Brian P. Ginsburg,et al. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC , 2005, 2005 IEEE International Symposium on Circuits and Systems.