Optimizing Bounded Model Checking for Linear Hybrid Systems

Bounded model checking (BMC) is an automatic verification method that is based on finitely unfolding the system's transition relation. BMC has been successfully applied, in particular, for discovering bugs in digital system design. Its success is based on the effectiveness of satisfiability solvers that are used to check for a finite unfolding whether a violating state is reachable. In this paper we improve the BMC approach for linear hybrid systems. Our improvements are tailored to lazy satisfiability solving and follow two complementary directions. First, we optimize the formula representation of the finite unfoldings of the transition relations of linear hybrid systems, and second, we accelerate the satisfiability checks by accumulating and generalizing data that is generated during earlier satisfiability checks. Experimental results show that the presented techniques accelerate the satisfiability checks significantly.

[1]  Joseph Sifakis,et al.  Specification and verification of concurrent systems in CESAR , 1982, Symposium on Programming.

[2]  Armando Tacchella,et al.  Benefits of Bounded Model Checking at an Industrial Setting , 2001, CAV.

[3]  Wojciech Penczek,et al.  Checking Reachability Properties for Timed Automata via SAT , 2002, Fundam. Informaticae.

[4]  Ofer Strichman,et al.  Accelerating Bounded Model Checking of Safety Properties , 2004, Formal Methods Syst. Des..

[5]  Armin Biere,et al.  Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs , 1999, CAV.

[6]  John B. Shoven,et al.  I , Edinburgh Medical and Surgical Journal.

[7]  Harald Ruess,et al.  Lazy Theorem Proving for Bounded Model Checking over Infinite Domains , 2002, CADE.

[8]  Navendu Jain,et al.  Verification of Timed Automata via Satisfiability Checking , 2002, FTRTFT.

[9]  E. Clarke,et al.  Verifying Safety Properties of a PowerPC TM 1 Microprocessor Using Symbolic Model Checking without BDDs , 1999 .

[10]  Harald Ruess,et al.  Bounded Model Checking and Induction: From Refutation to Verification (Extended Abstract, Category A) , 2003, CAV.

[11]  Thomas A. Henzinger,et al.  The theory of hybrid automata , 1996, Proceedings 11th Annual IEEE Symposium on Logic in Computer Science.

[12]  Howard Wong-Toi,et al.  Automated Analysis of an Audio Control Protocol , 1995, CAV.

[13]  L. D. Moura Lemmas on Demand for Satisfiability Solvers , 2002 .

[14]  Harald Ruess,et al.  An Experimental Evaluation of Ground Decision Procedures , 2004, CAV.

[15]  Edmund M. Clarke,et al.  Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.

[16]  Maria Sorea Bounded Model Checking for Timed Automata , 2002, Electron. Notes Theor. Comput. Sci..

[17]  Marco Bozzano,et al.  Verifying Industrial Hybrid Systems with MathSAT , 2005, BMC@CAV.

[18]  Thomas A. Henzinger,et al.  Automatic symbolic verification of embedded systems , 1993, 1993 Proceedings Real-Time Systems Symposium.

[19]  Sergey Berezin,et al.  CVC Lite: A New Implementation of the Cooperating Validity Checker Category B , 2004, CAV.

[20]  Rajeev Alur,et al.  A Theory of Timed Automata , 1994, Theor. Comput. Sci..

[21]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[22]  Piergiorgio Bertoli,et al.  A SAT Based Approach for Solving Formulas over Boolean and Linear Mathematical Propositions , 2002, CADE.

[23]  A. Tarski A Decision Method for Elementary Algebra and Geometry , 2023 .

[24]  Thomas A. Henzinger,et al.  The Algorithmic Analysis of Hybrid Systems , 1995, Theor. Comput. Sci..

[25]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[26]  Gilles Audemard,et al.  Bounded Model Checking for Timed Systems , 2002, FORTE.