A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models

This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables the analysis of influence of physical wire properties on the system performance and power dissipation in early design stages. SystemC provides the infrastructure to integrate transaction-level model and low-level models. By utilizing approximate timing, different temporal granularity can be used, leading to fast simulation speed. Six deep-submicron CMOS processes from 180 nm to 45 nm are used to evaluate the performance/power of NoC. Additionally, temporal and spatial NoC power analysis under different traffic conditions provides an effective basis for power/thermal optimization and design space exploration in early design stages.

[1]  Niraj K. Jha,et al.  A High-level Interconnect Power Model for Design Space Exploration , 2003, ICCAD 2003.

[2]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, MICRO.

[3]  Krste Asanovic,et al.  Replacing global wires with an on-chip network: a power analysis , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[4]  Sri Parameswaran,et al.  NoCGEN:a template based reuse methodology for Networks On Chip architecture , 2004, 17th International Conference on VLSI Design. Proceedings..

[5]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[6]  Nikil Dutt,et al.  Leakage Power Estimation in SRAMs , 2003 .

[7]  Jari Nurmi,et al.  VHDL-based simulation environment for Proteo NoC , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[8]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[9]  Giovanni De Micheli,et al.  A complete network-on-chip emulation framework , 2005, Design, Automation and Test in Europe.

[10]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[11]  Kees G. W. Goossens,et al.  Cost-performance trade-offs in networks on chip: a simulation-based approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.