9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

Noise shaping (NS) SAR ADCs combine the merits of SAR and Δσ ADCs, and can simultaneously achieve high power efficiency and high resolution. The key operation in an NS SAR is the residue integration. One way to implement it is to use a conventional closed-loop OTA [1]–[2]. It is robust against PVT variation and can realize a sharp noise transfer function (NTF), but it consumes static power and is does not scale easily. Another way is to use a passive filter [3]–[4]. It does not consume any static current, but its NTF is less aggressive. Moreover, because the gain of a passive filter is low, its suppression of the comparator noise is weak. An open-loop dynamic amplifier (DA) can be placed before the passive filter to reduce noise and power, but its gain varies with PVT [5]–[6]. To ensure stability, the NTF needs to be mild, which limits the NS performance [5], or background calibration has to be used, which increases the design complexity and requires a large number of samples to converge [6]. In addition, without complete settling, the gain of an open-loop DA is sensitive to timing error, e.g. clock jitter.

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[2]  Chun-Cheng Liu,et al.  28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[3]  Michael P. Flynn,et al.  A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC , 2012, 2012 IEEE International Solid-State Circuits Conference.

[4]  Nan Sun,et al.  A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting , 2019, IEEE Journal of Solid-State Circuits.

[5]  Nan Sun,et al.  An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier , 2019, 2019 Symposium on VLSI Circuits.

[6]  Ying-Zu Lin,et al.  20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[7]  Tien-Yu Lo,et al.  27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[8]  Nan Sun,et al.  A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[9]  Kofi A. A. Makinwa,et al.  A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier , 2018, IEEE Journal of Solid-State Circuits.