Nanoscale reconfigurable computing using non-volatile 2-D STTRAM array

In this paper, we investigate the combination of a novel computing paradigm referred to as Memory Based Computing (MBC) and an emerging non-volatile nanoscale memory technology, namely Spin-Torque Transfer Random Access Memory (STTRAM), to build a reconfigurable nanocomputing framework with high integration density, robustness and energy-delay efficiency. MBC uses a 2-D memory array as underlying computing element. Noting the read-dominant access pattern in MBC, we optimize the STTRAM cells to increase the energy-delay efficiency. Further, exploiting the asymmetric nature of the cells, we introduce the notion of preferential storage which optimizes the cell performance for ‘1’ over ‘0’ and skew the LUT content toward ‘1’ for improved energy-delay product (EDP).

[1]  H. Ohno,et al.  Current-Driven Magnetization Switching in CoFeB/MgO/CoFeB Magnetic Tunnel Junctions , 2005, INTERMAG 2006 - IEEE International Magnetics Conference.

[2]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  E. Belhaire,et al.  Integration of Spin-RAM technology in FPGA circuits , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[4]  Lionel Torres,et al.  New nonvolatile FPGA concept using magnetic tunneling junction , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[5]  Swarup Bhunia,et al.  Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches , 2008, ICCAD 2008.

[6]  Swarup Bhunia,et al.  MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices , 2008, 2008 Asia and South Pacific Design Automation Conference.

[7]  Swarup Bhunia,et al.  Reconfigurable computing using content addressable memory for improved performance and resource usage , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[8]  Jon M. Slaughter,et al.  Magnetoresistive random access memory using magnetic tunnel junctions , 2003, Proc. IEEE.

[9]  Shoji Ikeda,et al.  2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.